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Overview

CHIMES² — the Centre for Heterogeneous Integrated MicroElectronic and Semiconductor Systems — is one of the UK’s national semiconductor research-translation programmes, a £16.3M Innovation and Knowledge Centre led by the University of Sheffield. We are appointing a Research and Innovation Fellow in Systems Architecture and Design to its CTO Office.

This is not a conventional postdoctoral research post. Its core is landscape analysis and roadmap intelligence — reading the international state of the art in system architecture, chiplet partitioning and front-end design, identifying the gaps the UK must close, and turning that into the knowledge infrastructure a national programme runs on. A research theme of your own is developed alongside that work, not instead of it.

This post focuses on the ‘logical’ layer of heterogeneous integration — partitioning a system into functional chiplets and dies, specifying cross-die interfaces, and establishing the system-level architecture that determines what is integrated, how it is interconnected, and what performance, power and security properties the assembled system must deliver. This spans system-technology co-optimisation (STCO/XTCO), front-end design automation (RTL, logic synthesis, architectural exploration, floor planning, partition-aware EDA flows), chiplet interconnect standards (UCIe, CXL, die-to-die PHY), and the open Design Commons methodology CHIMES² is building as its core knowledge infrastructure.

We are advertising two paired CTO Office posts in parallel: in Systems Architecture and Design (the logical layer) and a companion post in Manufacturing Pathways, Test and Supply Chain (the physical layer). The logical-to-physical handoff — where system partitioning decisions are handed from architectural intent to physical realisation — is the primary interface between the two posts, and both post holders are expected to develop working familiarity with each other’s domain. Candidates whose interests span both layers are welcome to apply for both; please indicate this in your cover letter.

You will join the Microelectronics and Integrated Semiconductor Systems Team within the Quantum and Semiconductor Systems (QSS) Group — one of the UK’s largest and most successful semiconductor research environments. The Team hosts Sheffield’s leadership role for CHIMES², which brings together partner universities including Cambridge, Oxford, Edinburgh, Manchester, Newcastle, Strathclyde, Queen’s University Belfast and King’s College London, alongside the Science and Technology Facilities Council. Industrial partners include, among others, Imec, Arm, Pragmatic, Cadence, Synopsys and Siemens EDA. The CTO Office sits at the centre of the programme’s technical intelligence function; you will collaborate closely with the newly established CHIMES² engineering cohort, though the CTO Office and the engineering team are distinct functions.

Why this role is distinctive.

• It is a national-programme intelligence role. You will lead landscape and roadmap work that directly shapes CHIMES² research priorities, demonstrator projects, and the Design Commons — work with reach across the UK ecosystem, not confined to a single lab.
• It is a deliberate platform to launch from. The post is designed to let you build a visible, fundable independent research identity and the track record to launch it — whether toward a research fellowship (RAEng, UKRI FLF, MSCA, ERC Starting), a first permanent academic appointment, or a senior role in the national semiconductor ecosystem. The four-year term gives genuine room to figure out which of those is right for you and to become competitive for it.
• You will be a named representative of CHIMES² externally — at IMAPS, IEEE ECTC, DATE, Hot Chips, TechWorks DESN and equivalent forums — and a named author on Design Commons white papers, capability maps and policy briefings produced from your work.

Areas of particular interest for this post include:

• System partitioning and chiplet decomposition methodologies; cross-die interface specification frameworks.
• System-technology co-optimisation (STCO/XTCO) and mission-aware partitioning under power, thermal and security constraints.
• Front-end and system-level EDA for multi-die design — partition-aware synthesis, architectural exploration, system-level floor planning, cross-die timing, die-to-die interface IP.
• Chiplet interconnect standards (UCIe, CXL, die-to-die PHY) and interoperability frameworks (3Dblox, OIF).
• Open Design Commons infrastructure and open-source EDA / RISC-V IP ecosystems.

All four cross-cutting constraints — design-for-test (DfT), design-for-power-delivery (DfP), design-for-security (DfS) and design-for-thermal-extraction (DfTh) — span the logical-physical boundary, and both post holders are expected to develop working familiarity with them regardless of primary domain.

No candidate need span all areas. Strong credibility in logical systems architecture and front-end design is the core requirement; depth in one or more of the complementary areas above is welcomed.

We particularly welcome applicants whose work has bridged from adjacent backgrounds — computer architecture, embedded systems, FPGA-based research, accelerator or hardware-software co-design, low-power or sensor or quantum-hardware systems, or high-speed PCB / board-level integration — into circuit, system and integration work. To be clear, the focus is on the systems-and-integration direction; candidates whose current work is still on the device-physics or process side are out of scope for this post, as that capability is well covered elsewhere in the QSS Group, through CHIMES² partners (notably Imec), and through national semiconductor programmes.

Main duties and responsibilities

Technology landscape and roadmap

• Lead the WP1 logical systems architecture domain landscape activities — structured analysis of the needs of integrators and of those seeking to integrate maturing-TRL device, circuit or interposer propositions — covering system partitioning, chiplet decomposition, cross-die interface specification, and STCO/XTCO approaches across the UK and international HI community.
• Develop and maintain CHIMES² roadmaps for the logical architecture and front-end design domain, cross-referencing international roadmap assets including IEEE HIR, EU APECS, DARPA CHIPS/NGMM, SRC JUMP 2.0, imec STCO, and interoperability standards (UCIe / 3Dblox / OIF / CXL).
• Analyse front-end EDA tool gaps for heterogeneous integration — partition-aware synthesis, multi-die timing closure, DfT insertion at the chiplet boundary, DfS architectural patterns, power-intent specification across dies (UPF/CPF), and thermal-aware floorplanning.
• Conduct structured gap analysis identifying integration-specific design challenges underserved by current UK and international R&D, particularly in multi-vendor chiplet EDA flows, STCO, and open Design Commons infrastructure.

Leadership and ecosystem engagement

• Represent CHIMES² at national and international events and policy forums (IMAPS, IEEE ECTC, TechWorks DESN, DATE, Hot Chips and equivalent), and build relationships across the design, EDA, foundry/OSAT and standards communities (IEEE, JEDEC, IPC, SEMI, UCIe Consortium).
• Contribute technical intelligence to CHIMES² business and policy development — government consultation responses, policy briefings, and the programme’s strategic positioning — and communicate landscape findings to the Advisory and Technical Advisory Boards.
• Work collaboratively with domain-specific PDRAs recruited by CHIMES² Co-Investigators, aggregating contributions across the research college into coherent programme-level roadmap assets, and collaborate with the companion RIF on the logical-to-physical handoff methodology.
• Work closely with the CHIMES² Sheffield engineering team, contributing CTO Office intelligence to Design Commons and demonstrator delivery and to the programme’s skills-building activities.

Knowledge asset creation

• Lead the development of Design Commons white papers, capability maps and curated landscape reports in your domain, translating complex technical and ecosystem intelligence into outputs accessible to both technical and policy audiences.
• Apply and help shape the CHIMES² roadmapping methodology (technology roadmapping, systems thinking, gap analysis), ensuring outputs align with international benchmarks (IEEE HIR, EU Chips JU, DARPA NGMM, SRC JUMP 2.0).
• Contribute to co-created WP3 demonstrator project briefs and to Annual Reports, milestone deliverables and Flexible Funding call documentation.

Research, authorship and translation

• Develop an independent research theme arising from your landscape and roadmap work, with protected time agreed in the workplan at appointment and signed off by the CHIMES² Director. This theme is expected to intersect with CHIMES²’s heterogeneous-integration mission and to form the basis of future fellowship or first-academic-post applications.
• Be a named author on CHIMES² Design Commons white papers, capability maps and policy briefings, supported to develop these into peer-reviewed outputs and conference presentations.
• Collaborate with Co-Investigators and PDRAs to keep landscape work grounded in current research frontiers, and contribute to future funding applications and programme extensions.

• Carry out other duties, commensurate with the grade and remit of the post

Person Specification

Our community welcomes diverse backgrounds and experiences. We particularly encourage applications from researchers in their first postdoctoral position, and from researchers in a second postdoctoral role who would prefer a post of this kind to moving directly to a lectureship and from candidates whose work has bridged from adjacent backgrounds (materials, devices, sensors, photonics, RF, quantum hardware, FPGA, embedded systems, or high-speed PCB / board-level integration) into circuit, system and integration work. Even if your past experience doesn’t match perfectly with this role’s criteria, your contribution is valuable and we encourage you to apply. Please ensure that you reference the application criteria in your application statement.

Applicants must provide the following documents when making their application — please upload a merged PDF document under the cover letter section on our application system:

• CV (including a list of publications and / or technical outputs).
• A Research Vision Statement, setting out the independent research direction you would develop in this post and how it intersects with CHIMES²’s heterogeneous-integration mission — written so that it could form the seed of a future fellowship or first-academic-post application.
• A statement of up to three best outputs (peer-reviewed publications, or for candidates from industry, technical reports, standards contributions, or product / roadmap documentation that demonstrate the ability to produce high-quality written intelligence). For one of these, provide a short statement of no more than 100 words describing its originality, significance and rigour.

Key selection criteria include:

• Technical credibility in the logical systems architecture and front-end design domain (the primary shortlisting filter).
• Ability to synthesise and communicate complex technical intelligence to specialist and non-specialist audiences (the primary differentiator at interview, alongside technical depth).
• A credible, articulated independent research vision that intersects with CHIMES²’s mission.
• Ability to work across academic and industrial environments and to represent a national programme externally.

The full criteria are listed in the table below. No candidate need span all areas: we are looking for strength in the core domain competence plus depth in one or more of the named complementary areas.

Further Information

Next steps in the recruitment process

It is anticipated that the selection process will take place on week commencing 16/11/26. This will consist of an interview and a presentation. We plan to let candidates know if they have progressed to the selection stage on the week commencing 09/11/26. If you need any support, equipment or adjustments to enable you to participate in any element of the recruitment process you can contact eee-operations@sheffield.ac.uk.

Our vision and strategic plan

We are the University of Sheffield. This is our vision: sheffield.ac.uk/vision (opens in new window).

What we offer

• A minimum of 41 days annual leave including bank holiday and closure days (pro rata) with the ability to purchase more.
• Flexible working opportunities, including hybrid working for some roles.
• Generous pension scheme.
• A wide range of discounts and rewards on shopping, eating out and travel.
• A variety of staff networks, providing opportunities for social interaction, peer support and personal development (for example, Race Equality, LGBT+, Women’s and Parent’s networks).
• Recognition Awards to reward staff who go above and beyond in their role.
• A commitment to your development access to learning and mentoring schemes.
• A range of generous family-friendly policies
  • paid time off for parenting and caring emergencies
  • support for those going through the menopause
  • paid time off and support for fertility treatment
  • and more

More details can be found on our benefits page: sheffield.ac.uk/jobs/benefits (opens in a new window).

We are a Disability Confident Employer. If you have a disability and meet the essential criteria for this job you will be invited to take part in the next stage of the selection process.

Baseline personnel security standard

Some activities associated with this post may require the postholder to undertake a Government baseline personnel security standard (BPSS) check — for example, where landscape or roadmap work extends into defence-related areas. This is not a condition of appointment; where it applies, the University will support the postholder through that process.

Closing Date : 01/11/2026 

We are a research university with a global reputation for excellence. Our ideas and expertise change the world for the better, making a real difference to society. We know that when people come together with different views, approaches and insights it can lead to richer, more creative and innovative teaching and research and the highest levels of student experience. Our University Vision (www.sheffield.ac.uk/vision) outlines our commitment to building a diverse community of staff and students that recognises and values the abilities, backgrounds, beliefs and ways of living for everyone.